Low power integrated circuits (“ICs”), such as MOSFETs, are increasingly important due to the growing demand for battery-operated portable devices, such as cell phones. Long battery life requires minimal current flow, ideally no current flow, during the time the MOSFETs are “off” to minimize or eliminate unnecessary power consumption. FETs experience various types of undesirable “off” currents, including subthreshold currents, punch-through currents, oxide leakage currents, and currents caused by the Gate-Induced Drain Leakage (“GIDL”) effect, all of which result in undesirable current flow during MOSFET “off” times. The GIDL effect also deleteriously affects data retention time of DRAM arrays made up of MOSFETs.
Various studies of GIDL and its causes have been conducted. See, for example: “Comparison of GIDL in p+-poly PMOS and n+-poly PMOS Devices, by Lindert, et al., in IEEE Electron Device Letters, Vol. 17, No. 6, June 1996, pages 285-287; Silicon Processing for the VLSI Era, by Wolf, Vol. 3 (“The Submicron MOSFET”), Lattice Press, 1995, pages 198-200; Commonly assigned U.S. Pat. No. 6,144,075, issued Nov. 7, 2000, to the present inventor (the “'075” patent); and materials cited in the foregoing.
The '075 patent discloses a CMOS inverter implemented in and on a bulk substrate. Although past efforts have been directed towards eliminating GIDL, the '075 patent's inverter utilizes, rather than avoids, GIDL. Although the inverter of that patent has an integrated, MOS-like structure having a small layout, its operation is not based on the typical “MOS action,” i.e., action involving surface inversion and channel current.
A primary cause of GIDL is band-to-band tunneling that occurs at the substrate surface of a junction—source/substrate junction or drain/substrate junction—which is overlapped or overlain by a gate or a portion thereof. In a typical MOSFET, GIDL more commonly refers to unwanted “off” current associated with the drain/substrate junction.
The gate of an MOSFET is made up of a conductive gate electrode formed on a thin gate dielectric (usually an oxide) layer, which insulates the electrode from each junction and the intervening channel. A sufficiently large potential difference between the gate electrode and a drain, with the same polarity at the gate electrode as the majority carriers of the drain, results in a vertical field—i.e., a field that is across the gate oxide and is generally normal to the gate-substrate and gate-drain interfaces—that effects band bending at and near the conjunction of the interfaces. Band bending in the drain causes the minority carriers in the drain to tunnel from the valence band to the conduction band. A depletion region forms in the drain immediately subjacent to the gate oxide, and an inversion layer attempts to form at the surface of the drain adjacent the gate oxide. However, as minority carriers arrive at the drain surface to form the inversion layer, they immediately move, or are “swept,” to the substrate, which is a region of lower potential for them. As the minority carriers flow into the substrate, the resulting flow of excess majority carriers results in a leakage current, i.e., GIDL.
Voltage reference circuits utilizing MOSFETs are known, as shown, for example, in Analysis and Design of Analog Integrated Circuits, by Gray and Meyer, published by John Wiley and Sons (1984), pages 730-737 (“Gray and Meyer”). Specifically, Gray and Meyer describe a 5-FET threshold-voltage-referenced (Vt-referenced), self-biased reference circuit (FIG. 12.25a on page 732), noting that the circuit suffers from the fact that the threshold voltage of most MOSFETs is not particularly well controlled and the output has a large negative temperature coefficient. As an alternative to this circuit, Gray and Meyers describe a 2-MOSFET ΔVt-referenced circuit (FIG. 12.25b on page 732). The 2-MOSFET circuit uses the difference between Vt of two conventional FETs of the same polarity, but having different channel implants (e.g., enhancement-mode and depletion-mode, or, unimplanted enhancement-mode and implanted enhancement mode) and different Vt's.
Neuron-MOSFETs (or v-MOSFETs) are known. See the following U.S. Pat. Nos. 6,407,425 to Babcock, et al.; 5,806,054 to Bergemont, et al.; and 5,480,820 to Roth, et al. Also see “An Intelligent MOS Transistor Featuring Gate-Level Weighted and Threshold Operations,” by Shibata and Ohmi, in the proceedings of the 1991 International Electron Devices Meeting, pages 36.1.1 through 36.1.4. In addition to the foregoing, commonly assigned U.S. Pat. No. 6,133,780 to the inventor hereof shows a digitally tunable voltage reference using a neuron-MOSFET (the “'780 patent”).
A neuron-MOSFET includes a typical MOSFET having a source and a drain with an intervening channel. A conventional gate is formed over the channel by overlaying a gate oxide superjacent to the channel with a conductive electrode layer. The electrode layer extends laterally away from the MOSFET, where it is enlarged.
Two or more (1, 2 . . . N) separated, side-by-side, conductive input layers overlie the enlarged electrode layer extension and are separated therefrom by insulative layers, so that voltages (V) applied to the input layers are capacitively coupled to the enlarged electrode layer. The area, A1, A2 . . . AN, of each input layer may differ from the others, or some or all may have the same area. The coupling area (AC1, AC2 . . . ACN) of each input layer is the area of each input layer that is capacitively coupled with the enlarged electrode layer. The total area of the enlarged extension is much larger than the area of the gate electrode overlying the channel of the FET, and the total area of the enlarged electrode layer that is capacitively coupled to the input layers is ACT=AC1+AC2+ . . . ACN.
A coupling ratio is defined as R=AC/ACT, that is, R1=AC1/ACT, R2=AC2/ACT, . . . RN=ACN/ACT, and R1+R2+ . . . RN=1. The potential Vg of the gate electrode is the weighted sum of input voltages applied to the input layers, i.e., Vg=V1R1+V2R2+ . . . VNRN. When Vg is sufficiently high, the neuron-MOSFET turns “on,” and it may be said to be “fired.” A neuron-MOSFET, therefore, operates in an “if sufficient weighted sum, then fire” mode, a function that is relatively difficult to achieve with conventional static logic circuits, and which is said to mimic the “firing” of a neuron in the human brain.
The '780 patent describes a voltage reference circuit, after Gray and Meyer, substituting a neuron-MOSFET for one of the conventional MOSFETs. If the threshold voltage of the neuron-MOSFET and the conventional MOSFET are substantially the same, the output Vo of the circuit is equal to Vg, defined immediately above, as the weighted sum of the input voltages. Vo may, therefore, be tuned to one or more selected values, and various values of Vo may be obtained from different combinations of input voltages V1, V2 . . . VN.
Conventional MOSFETs, especially those fabricated pursuant to SOI protocols, suffer from a number of disadvantages. First, the inability to electrically connect to the substrate leads due to the “floating body effect,” in which charge becomes trapped between the gate dielectric and the BOX (“buried oxide”), an oxide buried in and bounding a region of a semiconductor layer to define the substrate. The floating body effect produces transient noise in the MOSFET.
Second, MOSFETs may exhibit “parasitic bipolar action” and “parasitic MOS action” due to the presence of forward-biased pnp/npn junctions and parasitic MOSFET channels. Third, the threshold voltage of MOSFETs may exhibit an unpredictable temperature-dependence. Fourth, as already noted, various undesirable leakage currents may occur in a MOSFET when it is in its “off” state. Fifth, fabricating a conventional FET requires that certain procedures be followed, such as using spacers during source and drain formation by diffusion or ion implantation; implementing lightly-doped drain formation steps prior to deep drain formation; and forming gate electrodes that conform to highly accurate critical dimensions. Sixth, the layout of a conventional MOSFET requires that a relatively large layout area be provided to accommodate both a source and a drain, as well as an intervening gate.